data-hazards

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

Pipelined RISC V 32 bit CPU in SystemVerilog

RISC-V RV32I 5-stage pipelined processor implemented in SystemVerilog with RTL design, testbench, and hex-based instruction memory.

Optimized RV32I processor with a 5-stage bypassed pipeline, hardware hazard mitigation, and same-cycle register file forwarding.

ECE552: Computer Architecture — Fall 2020.

A Python simulator for a simplified MIPS-lite ISA — decodes an instruction trace and models a 5-stage pipeline with optional forwarding, reporting instruction-mix statistics and final register/memory state.

C simulator for an 8-bit pipelined Harvard-architecture processor with assembly parsing, instruction encoding, hazard detection, and cycle-by-cycle execution tracing.

Implemented a RISC 5-stage pipeline in C++ and ran a benchmark program to observe a 60% reduction in total execution time between the pipelined and unpipelined design.

Superscalar CPU simulation models how modern processors execute instructions in parallel and manage hazards, analyzing and scheduling Python function instructions using advanced CPU features.

A Python RV32 RISC-V simulator with non-pipelined and five-stage pipelined execution modes, optional forwarding, cache modeling, and stage-by-stage instruction/register/memory traces.