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omermumtaz05/README.md

Hi there 👋

Hi there! My name is Omer Mumtaz and I'm currently a 3rd year undergrad student at the University of Toronto studying computer engineering. I'm currently working on learning computer hardware and ML. I'm passionate about computer hardware, AI, electronics and physics. Please email me at omer.mumtaz@mail.utoronto.ca to reach me! Thank you!

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  1. Pipelined_RISC_V_32_bit Pipelined_RISC_V_32_bit Public

    Pipelined RISC V 32 bit CPU in SystemVerilog

    SystemVerilog 3

  2. RISC-V-multicycle-32-bit RISC-V-multicycle-32-bit Public

    Multi-cycle 32-bit RISC V

    Verilog