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docs(H7): Portenta H7-only platform profile analysis + TODO H7-1..19 - #146
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Adds PLATFORM_H7.md for issue #141 (an X8-free build): base as an H7 USB radio gateway plus a PC, tractor H7 owning the Murata UART directly, and video from a second H7 (Vision Shield, or Nicla Vision for colour) linked over J5 SPI1 or Ethernet. Records the Max Carrier facts from the ABX00043 pinout (Murata on HD SERIAL3, modem on SERIAL1, RS-485 on SERIAL0, J4 camera FFC carrying the H7 DCMI lines) and a pull-model P0-P3 scheduling design between the two H7s. Adds the matching H7-1..19 items to DESIGN-CONTROLLER/TODO.md, including work that also helps the X8's onboard H747 (control app on Method G, four-class M7 TX queue, watchdog/fault capture, RNG, dual-bank images, MPU isolation), and links the doc from the DESIGN-CONTROLLER README. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JRs8sJLC6JbYLsSGM79Xcw
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🟡 Changes recommended
The design contains incorrect payload/test references and unresolved scheduling and timestamp-handling gaps.
4 open findings
What changed in this PR
Adds an H7-only controller profile addressing issue #141.
Changes:
- Documents H7-only base, tractor, camera, and scheduling architecture.
- Adds implementation tasks H7-1 through H7-19.
- Links the profile from the controller README.
| File | Description |
|---|---|
PLATFORM_H7.md |
Defines the proposed H7 architecture. |
TODO.md |
Adds implementation work items. |
README.md |
Links the new profile. |
🧠 Review effort: Balanced
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dorkmo
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Oct 13, 2026
Follow-up to #146: - State the VS1 fragment budget as the full TileDeltaFrame (<=203 B FHSS, <=243 B DTS, 6 B header + <=197/237 B body), not the body alone. - Fix the M7 throughput estimate: 32-83 ms x 5-15 gives ~0.16-1.25 s per frame (~0.8-6 fps) for the encode alone, before capture and pre-stage. - The L072 TX ring is pure FIFO; HOST_TXQ_P0_RESERVED is dead (RS-10.12), so the scheduler must keep non-P0 frames to HOST_TXQ_DEPTH-1 slots. - Stamp capture_ms from the camera's own capture tick via an offset learned from each request, not from the request time. - Point the VS1 port at the golden vectors in test_vector_codec.py; test_vs1_codec_parity_sil.py only checks the two Python copies match. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JRs8sJLC6JbYLsSGM79Xcw
dorkmo
pushed a commit
that referenced
this pull request
Oct 13, 2026
Follow-up to #146: - State the VS1 fragment budget as the full TileDeltaFrame (<=203 B FHSS, <=243 B DTS, 6 B header + <=197/237 B body), not the body alone. - Fix the M7 throughput estimate: 32-83 ms x 5-15 gives ~0.16-1.25 s per frame (~0.8-6 fps) for the encode alone, before capture and pre-stage. - The L072 TX ring is pure FIFO; HOST_TXQ_P0_RESERVED is dead (RS-10.12), so the scheduler must keep non-P0 frames to HOST_TXQ_DEPTH-1 slots. - Stamp capture_ms from the camera's own capture tick via an offset learned from each request, not from the request time. - Point the VS1 port at the golden vectors in test_vector_codec.py; test_vs1_codec_parity_sil.py only checks the two Python copies match. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JRs8sJLC6JbYLsSGM79Xcw
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Requested by Dorkmo · project thread
Before: the v25 controller design assumes a Portenta X8 on both the tractor and the base, and there is no written plan for the X8-free build that issue #141 asks for.
After:
DESIGN-CONTROLLER/PLATFORM_H7.mdlays out an H7-only profile, andDESIGN-CONTROLLER/TODO.mdhas a new "Portenta H7-only platform profile (H7)" section with items H7-1 to H7-19. The DESIGN-CONTROLLER README links the new doc.The doc covers the base as an H7 USB radio gateway plus a PC, the tractor H7 owning the Murata UART directly (which meets the MASTER_PLAN §8.10 intent better than the X8 does today), and tractor video from a second H7 (Vision Shield, or Nicla Vision for colour) linked over J5 SPI1 or Ethernet. It also gives a pull-model P0–P3 scheduling design between the two H7s. Max Carrier wiring facts come from the ABX00043 pinout and schematics already in the repo. Per that pinout, the Murata is on HD SERIAL3 and the cell modem on SERIAL1, which contradicts BRINGUP_MAX_CARRIER.md §1.1; TODO H7-1 tracks confirming and fixing that on hardware.
How: docs only, no code changes. The doc-reading SIL tests (
test_hardware_bom_xref_sil,test_build_config_doc_sil,test_cybersecurity_buildconfig_xref_sil,test_hil_harness_completeness_sil) pass locally.Refs #141
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