rtl-simulation

The open-source agentic RTL IDE

Agrionics Co.'s open source simulation and windows virtual development for intricate embedded developers

grep for waveforms — read signal values, clock frequency, and transitions from Synopsys FSDB, Cadence SST2, and open VCD dumps, straight from the shell. Deterministic output, runs locally, no viewer. CLI + MCP server + Claude Code skill.

This project implements a 4-bit pseudo-random number generator (PRNG) on the Basys 3 FPGA board using Verilog. The PRNG is designed using a Linear Feedback Shift Register (LFSR) with a tapped XOR feedback mechanism.

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

A CXXRTL cocotb simulator for SiliconCompiler — installed, not patched in. Built on cxxrtl-vpi.

Analysis of RISC-V Linux boot process using QEMU and OpenSBI with architectural state inspection for checkpointing research.

RTL implementation of an 8-bit sequential divider in SystemC featuring datapath/controller architecture, finite state machine control, testbench verification, and a signed divider extension using a bus interface.