questa-sim

Here are 7 public repositories matching this topic...

wyvernSemi / pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

Updated Jun 16, 2026
C

wyvernSemi / usbModel

Star

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

usb vhdl verilog vivado systemverilog icarus-verilog ghdl nvc xsim cosimulation cmodel questa-sim

Updated Oct 15, 2024
C++

wyvernSemi / tcpIpPg

Star

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

simulation verification verilog vivado ethernet icarus-verilog ghdl tcp-ip verilator nvc 10g xsim virtual-processor xgmii questa-sim

Updated Jan 28, 2025
C++

gopro-uvm-rtl-verification / Async-Fifo-Cdc-Uvm-Verification

Star

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim

Updated Aug 22, 2025
SystemVerilog

jsphtkn / uvm-uart-verification

Star

Industrial-grade UVM 1.2 environment for a full-duplex UART controller. Features Constrained Random Verification (CRV), weighted stress-testing, and multi-baudrate regression (9600–115200) using Questa Sim.

rtl uart systemverilog uvm digital-design uvm-verification questa-sim constrainted-randomization

Updated Feb 14, 2026
SystemVerilog

eleanazeri / IEEE754-SP-Multiplier-RTL

Star

RTL implementation of a 32-bit IEEE-754 single-precision floating-point multiplier in SystemVerilog, featuring SVA-based property checking

systemverilog floating-point ieee-754 digital-design sva hardware-verification rtl-design fp32 questa-sim

Updated Feb 24, 2026
SystemVerilog

Abdelwakil-Mansour / AES-128-Hardware-Accelerator

Star

Implementation AES-128 encryption using a single reusable round datapath, registered state and key storage, on-the-fly key expansion, and a four-state FSM-based controller. All ten AES rounds share one combinational datapath; resource reuse is traded for throughput relative to a fully unrolled or pipelined design.

encryption fpga verification verilog aes-encryption modelsim hardware-acceleration verification-methodologies test-bench digital-design ic-design 128-bit rtl-design hardware-architecture hardware-design questa-sim

Updated Aug 28, 2026
Verilog

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