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opensta

Here are 23 public repositories matching this topic...

vsdip / vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

Updated Jul 21, 2020
Coq

kanndil / PathView

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

eda primetime critical-path-analysis pathview static-timing-analysis opensta schematic-layout electronic-design

Updated Oct 22, 2024
HTML

Pa1mantri / Digital-Design-and-Synthesis

Pre and Post Synthesis Simulation of a Design VSDMemSOC

riscv gtkwave verilog-hdl yosys iverilog digital-design opensta

Updated May 30, 2025
Verilog

Silimate / liberty2json

Liberty to JSON converter

converter json liberty opensta

Updated Sep 3, 2026
Verilog

oscc-ip / artifact

A repository provides build artifacts for various open-source EDA tools.

opensta ieda

Updated Apr 14, 2026

Pa1mantri / VSDMemSoc-Physical-Design

VSDMemSOC PnR flow:: RTL2GDSII

macros riscv yosys gdsii physical-design openroad opensta openlane-flow sram-macro

Updated Mar 1, 2024
Verilog

Pa1mantri / NASSCOM_SoC_Design

Complete RTL to GDSII flow of a picorv32a core

opensource opensta rtl2gds openlane-flow

Updated Jun 6, 2025

3more102 / lenet5-asic-accelerator

Verified LeNet-5 int8 inference datapath in SystemVerilog, with a bit-exact Python oracle and real sky130hd PPA (pre-layout).

asic verification rtl systemverilog yosys digital-design lenet-5 static-timing-analysis openroad cnn-accelerator opensta sky130

Updated Aug 18, 2026
SystemVerilog

Olajide-Badejo / Low-Power-Async-CDC-FIFO-IP

Parameterized asynchronous CDC FIFO IP: gray-code pointers, a sweepable N-flop synchronizer, IEEE 1801 UPF low-power intent, SymbiYosys formal proofs, and a 60-config Yosys/OpenSTA PPA sweep on SkyWater Sky130. Fully open-source and reproducible.

asic rtl systemverilog fifo cdc formal-verification yosys digital-design low-power upf clock-domain-crossing static-timing-analysis opensta symbiyosys open-source-eda sky130

Updated Jul 16, 2026
SystemVerilog

karder1 / openroad-counter-rtl-to-gds

8-bit counter RTL-to-GDSII physical design using OpenROAD-flow-scripts and Nangate45.

asic verilog gtkwave vlsi yosys physical-design openroad opensta rtl-to-gds nangate45

Updated Jul 20, 2026
Tcl

Brafamous / uart-safety-controller-synthesis-sta

UART Safety Controller ASIC implementation project demonstrating RTL synthesis, SKY130 technology mapping, multi-corner static timing analysis (TT/SS/FF), timing closure, CDC/RDC review, and implementation readiness for ASIC physical design.

asic eda rtl verilog uart cdc vlsi yosys semiconductor digital-design ic-design static-timing-analysis physical-design rdc timing-closure opensta openlane sky130

Updated Jun 26, 2026
Verilog

ajayasai / OpenConstraint

Auditable, deterministic SDC constraint-quality checks and structural coverage for CI.

lint ci eda verilog sdc sarif static-timing-analysis opensta

Updated Sep 9, 2026
Python

NikhilRamanathan / 64bit-Multiplier-Architecture

Comparative RTL-to-gate level PPA analysis of 64-bit Array, Radix-4 Booth, and Dadda multipliers using SKY130 open-source ASIC tools

verilog systemverilog vlsi yosys digital-design multiplier opensta sky130

Updated Jul 4, 2026
Verilog

Varnish24 / custom-multicorner-sta

Custom Liberty-driven multi-corner static timing analysis engine for SKY130, validated against OpenSTA.

python asic eda vlsi yosys static-timing-analysis opensta sky130

Updated Sep 2, 2026
Python

karder1 / openroad-gcd-rtl-to-gds

RTL-to-GDSII physical design flow for the GCD design using OpenROAD-flow-scripts and Nangate45.

asic vlsi operand yosys nan physical-design opensta rtl-to-gds nangate45

Updated Jul 18, 2026
Verilog

karder1 / openroad-alu-rtl-to-gds

8-bit ALU RTL-to-GDSII physical design using OpenROAD-flow-scripts and Nangate45.

asic verilog alu gtkwave vlsi yosys physical-design openroad opensta rtl-to-gds nangate45

Updated Jul 22, 2026
Verilog

SandeepGorrepati / synth-sta

RTL synthesis (Yosys) + OpenSTA static timing analysis flow: gate-level netlist, area & critical-path, SDC constraints, WNS/TNS.

asic rtl verilog synthesis vlsi yosys sta opensta

Updated Jun 26, 2026
Verilog

RF746 / physical-design-convergence-analytics

Python CLI for comparing timing, area, utilization, DRC, and clock metrics from sanitized OpenROAD/OpenSTA-style reports.

python eda static-timing-analysis physical-design openroad opensta

Updated Aug 18, 2026
Python

Brafamous / 8_bit_CPU_RTL_Synthesis

8-bit CPU RTL synthesis flow using Verilog, Yosys, SKY130 standard cells, OpenSTA timing analysis, and ASIC-readiness documentation.

asic rtl verilog vlsi yosys digital-design cpu-design opensta openlane sky130 rtl-synthesis

Updated Jun 26, 2026
Verilog

Zhungg / rv32i-cpu-openlane

RV32I 5-stage pipelined CPU core implemented in SystemVerilog and taken through a complete Sky130A RTL-to-GDSII flow using OpenLane 2 and OpenROAD.

Updated Aug 13, 2026
Verilog

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