A flexible framework for analyzing and transforming FPGA netlists. Official repository.
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Updated
Apr 27, 2026 - Python
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
TMR utilities for the SpyDrNet project
OrCAD 회로도(EDIF/.DSN)를 KiCad 프로젝트로 변환하고 PADS 넷리스트로 검증하는 오픈소스 도구 | Open-source OrCAD to KiCad schematic converter with PADS netlist verification
MCP server for querying EDIF netlist files — components, nets, pin-level connectivity
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