Experiments to simulate multiple cache hierarchies, L1/L2 set-associativities, block sizes using DineroIV, and measure impact on Cycles Per Instruction (CPI) and Average Memory Access Time (AMAT).
A CPU benchmark suite that shows its work. Six workloads, calibrated measurement windows, barrier-synchronised threads, robust statistics, full machine provenance, and Ed25519-signed results.
Multiprocessor Simulator with two levels of Cache hierarchy.
A high-performance MIPS processor simulator written in Rust, featuring both functional and advanced timing simulations. Explore pipelined execution, Tomasulo's algorithm for out-of-order execution, multi-level cache hierarchies, and sophisticated branch prediction. Ideal for computer architecture education, research, and CPU design.
Superscalar pipeline simulator features out-of-order execution, MSHR-based cache, and cycle-accurate power modeling.
Configurable L1+L2 cache hierarchy simulator with LRU replacement and write-back/write-allocate policy, written in C++
An open-source live telemetry and system modeling engine for generative AI. Track total system resource utilization in real time across storage, memory paths, and compute blocks to eliminate black-box execution failures and accelerate the development of next-generation AI and generative AI architectures.
A from-scratch C++ implementation of a cache-aware CPU scheduler featuring score-based task selection, starvation prevention, and L1/L2/L3 cache simulation.
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