Hello There! It's a repository showcasing my CSE2114 (Computer Architecture Sessional) project. The task was to build a 29 bit computer with at least 4 instructions. As it was an open ended project I added some extra objectives.
- Building a computer with instruction set similar to RISC-V , in Harvard architecture
- Make the computer five stage pipelined
- The computer should support IO device interfacing
- Design A compiler, the compiler should provide higher level functionalities such as push/pop,mov etc.
- Code a snake game
- Design preset bootloader and interrupt set
Open the CPU.circ file in Logisim Evolution. Write assembly codes following the Assembly Manual and compile/assemble using the compiler (Requires NodeJS).
./translate file.asm
The details on the hardware design can be found here. Learn about the Compiler Design
- The r0 has a fixed value : 0 , which is useful for implementing various high level features such as mov or jz. The r16 produces random value.
- In case of jumps the later 3 instructions must be replaced with nop
- Cache was not added as it'd require interrupt management system and slow down the computer
- No register on WB - Memory (As memory already takes one clock extra), May need to add buffer on every IO
- While debugging hard errors can be detected by checking current status (line status); most hard errors are delay related. In case of soft error / resource conflict, it must be resolved by the assembler (pause command in case of conflict, if placable place other instruction else place nop).
- Wikipedia - RISC-V
- The RISC-V Instruction Set Manual
- Stack Overflow - How to implement CISC Pipeline
- ResearchGate - RISC-V
- Wikipedia - Clasic RISC Pipeline
- Berkeley - RISC-V CPU Control, Pipelining
- RISC-V Pipeline Implementation
- Cornell - RISC-V Interpreter
- Washington - Pipelining
- FSU - Pipelined Datapath