Add display support for nord - #1034
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Shiraz Hashim (shashim-quic) merged 10 commits intoSep 2, 2026
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| #define DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4 | ||
| #define DP_QSERDES_V8_COM_CMN_STATUS 0x314 | ||
| #define DP_QSERDES_V8_COM_C_READY_STATUS 0x33c | ||
| #define DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL_V2 0x17c |
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in diff it shows like this because of tab, but in code its fine, aligned properly.
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Add the compatible for the eDP PHY found on the Qualcomm Nord SoC. Signed-off-by: Mahadevan P <mahap@qti.qualcomm.com>
Add the compatible for the DisplayPort controller found on the Qualcomm Nord SoC. Signed-off-by: Mahadevan P <mahap@qti.qualcomm.com>
Add the binding for the display subsystem (MDSS) found on the Qualcomm Nord SoC. Nord is MDSS 12.1, DP-only (no DSI), with two independent DP controllers. Signed-off-by: Mahadevan P <mahap@qti.qualcomm.com>
Add the DPU catalog entry for the Qualcomm Nord SoC (MDSS 12.1, DPU 1499A). Nord is DP-only with no DSI, and provides 8 DSPP blocks, 2 writeback blocks, 8 interfaces and 2 DP controllers. Extend enum dpu_intf with INTF_9 and INTF_10, which Nord is the first platform to use. Note: register addresses and xin_id values in the catalog are borrowed from sm8750 and precedent platforms and are marked with FIXME(REG_ADDR) and FIXME(XIU_MAP); they need verification against a real Nord register map before production use. Signed-off-by: Mahadevan P <mahap@qti.qualcomm.com>
Add the MDSS compatible for the Qualcomm Nord SoC, reusing the 57 MBps register bus bandwidth setting shared with the other recent platforms. Signed-off-by: Mahadevan P <mahap@qti.qualcomm.com>
Add the DP controller description and compatible for the Qualcomm Nord SoC, which provides two independent DP controllers, both wide-bus capable. Signed-off-by: Mahadevan P <mahap@qti.qualcomm.com>
Add the MDSS, DPU, DP0/1 controllers and eDP0/1 PHY nodes for the Qualcomm Nord SoC. Nord is DP-only, so no DSI nodes are added. Wire the DP PHY outputs into the dispcc0 clock inputs, which were previously stubbed with zeroes. Signed-off-by: Ritesh Kumar <riteshk@qti.qualcomm.com>
Enable the MDSS, DP0/1 controllers and eDP0/1 PHYs on the Nord Ride SX board and describe the eDP0 connector, its 4 data lanes and supported link frequencies. Signed-off-by: Ritesh Kumar <riteshk@qti.qualcomm.com>
Enable the MDSS, DP0/1 controllers and eDP0/1 PHYs on the Nord Ride SX board and describe the eDP0 connector, its 4 data lanes and supported link frequencies. Signed-off-by: Ritesh Kumar <riteshk@qti.qualcomm.com>
Add support for the eDP PHY found on the Qualcomm Nord SoC, including the AUX and VCO_DIV configuration, the eDP and DP swing/pre-emphasis tables and the Nord specific PLL, SSC, LDO and reset sequences. Signed-off-by: Ritesh Kumar <riteshk@qti.qualcomm.com>
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| oneOf: | ||
| - enum: | ||
| - qcom,glymur-dp-phy | ||
| - qcom,nord-dp-phy |
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keep entries sorted.
| oneOf: | ||
| - enum: | ||
| - qcom,glymur-dp | ||
| - qcom,nord-dp |
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same, should be sorted.
Shiraz Hashim (shashim-quic)
merged commit Sep 2, 2026
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Add display support for NORD.