riscv64: Implement Remaining Vector Instructions

👋 Hey,

This is a general issue for tracking the missing instructions from the RISC-V Vector extension. We have implemented most of them, however there are a couple of categories that are still missing

## Widening and Narrowing Operations

- [x] [Vector Widening Integer Add/Subtract](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#112-vector-widening-integer-addsubtract)
- [ ] [Vector Widening Integer Multiply Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1112-vector-widening-integer-multiply-instructions)
- [ ] [Vector Narrowing Integer Right Shift Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#117-vector-narrowing-integer-right-shift-instructions)
- [ ] [Vector Widening Integer Multiply-Add Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1114-vector-widening-integer-multiply-add-instructions)
- [ ] [Vector Widening Floating-Point Add/Subtract Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#133-vector-widening-floating-point-addsubtract-instructions)
- [ ] [Vector Widening Floating-Point Multiply](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#135-vector-widening-floating-point-multiply)
- [ ] [Widening Floating-Point/Integer Type-Convert Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1318-widening-floating-pointinteger-type-convert-instructions)
- [ ] [Narrowing Floating-Point/Integer Type-Convert Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1319-narrowing-floating-pointinteger-type-convert-instructions)
- [ ] [Vector Widening Floating-Point Fused Multiply-Add Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#137-vector-widening-floating-point-fused-multiply-add-instructions)


I have Implemented [Vector Widening Integer Add/Subtract](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#112-vector-widening-integer-addsubtract) in #6542 and #6555.

I also have a branch that contains [Vector Widening Integer Multiply Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1112-vector-widening-integer-multiply-instructions) in [riscv-simd-widening-mul](https://github.com/afonso360/wasmtime/tree/riscv-simd-widening-mul), however before merging that I think it we should rework our approach towards these instructions.

Matching one of these instructions includes a lot of rules mostly due to how many combinations we can perform with `{s,u}widen_{low,high}`, so before adding any more instruction I think we need to add an extractor that can match all of these patterns.

As an example `vwmulsu.vv` requires 8 rules to match all combinations of `{s,u}widen_{low,high}`.

## Vector Multiple Register Move

We have implemented `vmv1r.v` as our move instruction, this instruction moves one register into another. However we also have `vmv2r.v` / `vmv4r.v` / `vmv8r.v`. These instructions move n consecutive registers.

As an example, `vmv2r.v v10, v12` copies `v10=v12; v11=v13`.

These instructions have a constraint that the source and destination registers must be "aligned" to the number of the instruction. `vmv2r.v v11, v15` would be an illegal instruction.

- [ ] [Whole Vector Register Move](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#166-whole-vector-register-move)

## Vector Reduction Operations

- [ ] [Vector Single-Width Integer Reduction Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#141-vector-single-width-integer-reduction-instructions)
- [ ] [Vector Widening Integer Reduction Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#142-vector-widening-integer-reduction-instructions)
- [ ] [Vector Single-Width Floating-Point Reduction Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#143-vector-single-width-floating-point-reduction-instructions)
- [ ] [Vector Widening Floating-Point Reduction Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#144-vector-widening-floating-point-reduction-instructions)

I'm not entirely sure how we can best match these operations. We don't have the equivalent instructions in cranelift.

These instructions do a operation on an entire vector register, such as a sum and return a scalar value. We have two of these implemented `vredminu` and `vredmaxu`  that are used when lowering `vany_true` or `vall_true`.

## Special Load / Store Addressing Modes

We currently implement [Vector Unit-Stride Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions) for all our Loads and Stores. These are fairly simple in that they load `vl` elements that are a fixed number of bits apart. These match the semantics of the `load` and `store` instructions in cranelift.

The remaining Addressing Modes might be beneficial, but I have no idea how we could match them. Some of these might not be that useful.

- [ ] [Vector Strided Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions)
- [ ] [Vector Indexed Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions)
- [ ] [Unit-stride Fault-Only-First Loads](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads)
- [ ] [Vector Load/Store Segment Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#78-vector-loadstore-segment-instructions)
- [ ] [Vector Load/Store Whole Register Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions)

## Vector Integer Division

We don't actually support vector `sdiv` / `udiv`, nevertheless RISC-V includes instructions for them in [Vector Integer Divide Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1111-vector-integer-divide-instructions). I'm including this here mostly for completeness.

- [ ] [Vector Integer Divide Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1111-vector-integer-divide-instructions)

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riscv64: Implement Remaining Vector Instructions #7186

Widening and Narrowing Operations

Vector Multiple Register Move

Vector Reduction Operations

Special Load / Store Addressing Modes

Vector Integer Division

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riscv64: Implement Remaining Vector Instructions #7186

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Widening and Narrowing Operations

Vector Multiple Register Move

Vector Reduction Operations

Special Load / Store Addressing Modes

Vector Integer Division

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Metadata

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