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Allow passing custom module name to output_to_verilog - #474

Merged

fdxmw merged 12 commits into

UCSBarchlab:developmentfrom

devmam999:feature/module_name_param

Nov 17, 2025

Merged

Allow passing custom module name to output_to_verilog#474
fdxmw merged 12 commits into
UCSBarchlab:developmentfrom
devmam999:feature/module_name_param

Commits on Oct 21, 2025
- Allow passing custom module name to output_to_verilog
  dmamidi-ux
  committed
  caeb04b
Commits on Oct 25, 2025
- Update module declaration and add module_name option
  devmam999
  authored
  d6e803b
Commits on Oct 28, 2025
Commits on Nov 4, 2025
- module_name is now a class parameter
  devmam999
  committed
  c64298e
Commits on Nov 5, 2025
- Added module_name as a parameter to a few functions as necessary
  devmam999
  committed
  6113e6d
Commits on Nov 7, 2025
- Merge branch 'development' into feature/module_name_param
  devmam999
  authored
  236f290
Commits on Nov 11, 2025
- Added a test for my change
  devmam999
  authored
  b18009c
Commits on Nov 13, 2025
- Fixed issues and improved placement of my tests
  devmam999
  authored
  52d3f43
Commits on Nov 15, 2025
- Merge branch 'UCSBarchlab:development' into feature/module_name_param
  devmam999
  authored
  5307dc8
- Fixed formatting errors
  devmam999
  committed
  c252752