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@SiliconLanguage

SiliconLanguage

Architecting post-Von Neumann AI infrastructure. We build 0-kernel, 0-copy, NVMe-oF data planes, and hardware-software co-designed frameworks for hyperscale.
README.md
SiliconλLanguage Delta

Architecting post-Von Neumann AI infrastructure.


📖 Read The Tensorplane Manifesto

⬛ The Monadic Paradigm

As generative AI models scale into the trillions of parameters and agentic workflows demand real-time state manipulation, traditional OS kernels have become the primary bottleneck. We build 0-kernel, 0-copy, NVMe-oF data planes and bare-metal virtualization frameworks that fuse compute, memory, and I/O into a single, deterministic fabric.

By treating the host CPU as a pure computational engine and offloading side-effects to hardware-accelerated structures, we eliminate context-switching jitter and feed AI accelerators at line rate.

⚡ Core Infrastructure Foundry

  • tensorplane: (In Development) The Agentic Control Plane. A Recursive Self-Improving AI Foundry driven by a Multi-Agent System (MAS) operating over the Model Context Protocol (MCP). It autonomously monitors telemetry, dynamically provisions cloud infrastructure, and orchestrates the underlying data planes.
  • dataplane-emu: A hardware-accurate C++ emulation framework for direct-to-silicon data planes. Enables transparent POSIX interception (LD_PRELOAD) to route legacy workloads directly into user-space queues without application rewrites.
  • 🌀 ueXRP: The User-Mode eXtended eXpress Resubmission Path. A user-space eBPF storage engine and DPU-offload framework (XRP Direct) extending the Double Trampoline data plane. By embedding eBPF virtual machines (uBPF/Aya) directly into lock-free SPDK polling loops, it executes complex on-disk data structure traversals without relying on kernel interrupts. It leverages a user-space Metadata Digest and NVIDIA BlueField-3 SNAP to offload storage logic entirely to the DPU, eliminating the PCIe traversal tax and achieving true zero-host-CPU orchestration for unmodified POSIX workloads.
  • monadic-hypervisor: (In Development) A mathematically verifiable, bare-metal virtualization architecture. It treats the host CPU as a pure computational engine by shifting all network and storage "side-effects" to out-of-band DPUs (e.g., NVIDIA BlueField-3). It leverages Scalable I/O Virtualization (SIOV) and PASID tracking to multiplex PCIe devices across hyperscale multi-tenant boundaries without host-CPU emulation overhead.
  • ⚡🧠 m-store: The Unified Memory & State Orchestration Fabric. A zero-kernel, RDMA-first data plane designed to eliminate the AI "memory wall." m-store natively integrates with inference frameworks like vLLM (PagedAttention) and SGLang (RadixAttention) to provide a disaggregated Key-Value (KV) cache substrate. By leveraging SPDK and CXL 3.1 Global Integrated Memory, it completely bypasses the Linux kernel to swap massive context windows directly into GPU VRAM at bare-metal speeds.
  • m-ipc: A bare-metal, hardware-assisted messaging framework. Built for RISC-V many-core scaled-up clusters to eliminate the "synchronization tax" using cache-pollution mitigation and zero-copy semantics.

🔬 Architecture & Research

We actively research and engineer at the intersection of:

  • Bare-Metal Virtualization: Scalable I/O Virtualization (SIOV) and DPU/SmartNIC offloading.
  • Hardware-Software Co-Design: ARM64 (Graviton) weak memory ordering optimizations and RISC-V custom extensions.
  • Zero-Trust Agentic Gateways: Deterministic, hardware-isolated Model Context Protocol (MCP) routing.
root@silicon-lang:~# ./init_foundry.sh

Pinned Loading

  1. dataplane-emu dataplane-emu Public

    A hardware-accurate C++ data plane emulator for high-performance storage and networks. Simulates lock-free SPDK/io_uring queues, DPDK-style thread-per-core execution, and NVMe-oF architectures

    C++ 2

  2. mempool mempool Public

    Forked from pulp-platform/mempool

    MemPool-IPC: Hardware-Assisted Monadic Messaging Framework, forked from MemPool, a scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

    C

  3. monadic-hypervisor monadic-hypervisor Public

    A bare-metal, zero-kernel Type-1 hypervisor for the device-edge-cloud continuum. Written in Rust for ARM64 (EL2) and RISC-V, it enables true PCIe bypass and hardware-hardened OS services to elimina…

    Rust

Repositories

Showing 10 of 15 repositories
  • solitude Public

    An integrated compiler and hardware co-design stack for high-dimensional, non-associative algebras (octonion, exceptional Jordan algebra, Albert algebra) based compute. Adopting the Sounio systems language specification to implement a custom MLIR dialect (sounio.nonassoc) that disables associative optimizations, paired with simulators for Fano ALUs

    SiliconLanguage/solitude's past year of commit activity
    Python 0 Apache-2.0 0 0 0 Updated Aug 23, 2026
  • dataplane-emu Public

    A hardware-accurate C++ data plane emulator for high-performance storage and networks. Simulates lock-free SPDK/io_uring queues, DPDK-style thread-per-core execution, and NVMe-oF architectures

    SiliconLanguage/dataplane-emu's past year of commit activity
    C++ 2 Apache-2.0 0 0 0 Updated Jul 12, 2026
  • tensorplane Public

    An enterprise-grade AI data plane accelerator achieving true zero-copy I/O. Inspired by DeepSeek 3FS USRBIO, it separates command and data queues for GPUDirect RDMA streaming and SmartNIC/DPU offloading, bypassing POSIX bottlenecks for hyperscale AI workloads.

    SiliconLanguage/tensorplane's past year of commit activity
    Rust 1 BSD-2-Clause-Patent 0 0 0 Updated May 28, 2026
  • 0kernel Public
    SiliconLanguage/0kernel's past year of commit activity
    TypeScript 0 0 0 0 Updated May 21, 2026
  • nanochat Public Forked from karpathy/nanochat

    Andrej Karpathy's nanochat fork, implementing a 0-kernel "Overlay Architecture." Shatters I/O bottlenecks via LD_PRELOAD SPDK polling, GPUDirect Storage (GDS) for zero-cost checkpointing, and Custom Triton DSL kernels to saturate Hopper TMA.

    SiliconLanguage/nanochat's past year of commit activity
    Python 0 MIT 8,207 0 0 Updated May 5, 2026
  • model-explorer-open-llm Public

    A hybrid testbed for evaluating top open-source LLMs (like gpt-oss-20b and Llama 3.3) on local, cloud GPUs, and AWS Inferentia2/Trainium instances, focusing on vLLM optimization, capacity management, kernel bypass, hardware-software co-design, as well as supporting infrastructure such as NCCL, RDMA, NVMeoF.

    SiliconLanguage/model-explorer-open-llm's past year of commit activity
    Python 0 Apache-2.0 0 0 0 Updated Apr 21, 2026
  • asr-serve Public

    A zero-kernel AI speech-to-text inference engine. Routes active speech via Graviton4 VAD (eBPF/XDP) to hybrid Inferentia/GPU ASR tier. Orchestrated by NVIDIA Dynamo for Prefill-Decode Disaggregation (PDD), vLLM & Blackwell NVFP4 optimizations. Governed by the Adaptive Agentic AI foundry platform evaluating state-of-the-art open-source ASR models.

    SiliconLanguage/asr-serve's past year of commit activity
    Python 0 0 0 0 Updated Apr 20, 2026
  • ueXRP Public

    A user-space eBPF storage engine (uXRP) and DPU-offload framework (XRP Direct) extending the Double Trampoline data plane. Integrates uBPF/Aya into lock-free SPDK polling loops for zero-tax NVMe resubmission, bypassing the kernel while maintaining POSIX compatibility via an LD_PRELOAD shim.

    SiliconLanguage/ueXRP's past year of commit activity
    C++ 0 0 0 0 Updated Apr 19, 2026
  • .github Public

    Special repository to add a README.md to public organization profile, visible to anyone.

    SiliconLanguage/.github's past year of commit activity
    0 0 0 0 Updated Apr 19, 2026
  • model-explorer-open-asr Public

    A hybrid testbed for evaluating top open-source ASR models (Cohere, Qwen3-ASR, IBM Granite) featuring vLLM server-side routing and transformers.js WebGPU client-side inference.

    SiliconLanguage/model-explorer-open-asr's past year of commit activity
    Python 0 Apache-2.0 0 1 0 Updated Apr 15, 2026
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