I've taken two RTL designs through verification to FPGA place-and-route, and I write C++20 for vehicle simulation and multicore machines.
- Cellular-automaton accelerator for a RISC-V SoC: a SystemVerilog drawing unit with 100% statement, branch, condition and FSM coverage in Questa, placed and routed on Artix-7. My self-checking testbench flagged 4 of 5 supplied drawing units as faulty.
- Stump 16-bit RISC CPU: a multi-cycle Verilog CPU on Spartan-6, for which I built the datapath, ALU, shifter, register file and control FSM around a supplied board wrapper and memory model.
- FSAI driverless simulator: I led the 10–15 person Formula Student driverless sub-team for three years and wrote about 29k of the 34k lines of its C++20 simulator. Its CAN layer is all mine: a bit-level codec for 14 ADS-DV messages over SocketCAN, tested against a simulated VCU.
- Chip Multiprocessors labs: I fixed four synchronisation bugs in a supplied stencil, then added temporal blocking to reach 132× over serial on 72 threads.
My HDL is university coursework, so the source stays private; the portfolio has the write-ups.
Currently: MSc Computer & Embedded Systems Engineering at TU Delft, graduating 2028.