Feature Request: Analyze verilog files for NVC

[a-panella]

Hi Jim,

NVC currently has preliminary support for verilog (nvc version: 1.22-devel) , allowing us to now do mixed-language simulation in FOSS simulator :)

Can we please get the ability to analyze verilog files in Osvvm for NVC? It seems you already support verilog analysis for other (commercial) simulators

Currently, when attempting to do mixed language simulation with Osvvm Scripts + NVC, the verilog files get the message and analysis is skipped, leading to no binding indication for the entity:

analyze meme.v
Analyzing verilog files not supported by NVC

Thanks for your time!

[JimLewis]

Should be done with #85
Let me know how it goes and close this if that addresses it.

This is on the dev branch. Will be released with 2026.07.

These things are done in the file OsvvmLibraries/Scripts/VendorScripts_NVC.tcl
If you know how to do the settings for code coverage, it should not be a too difficult edit to add it to the script. I am looking for someone who would like to do a pull request for it.