NVMe rejects any controller whose CAP.MPSMIN is not exactly 4K, and never programs CC.MPS. admin/controller.rs:34 returns UnsupportedPageSize unless min_page_shift()==12, then writes CC without setting CC.MPS (bits 7:11), leaving host page size at 4K by default. The computed max_page_shift is never used.
Nearly all real SSDs advertise MPSMIN=0 so the == gate usually passes, but any controller advertising MPSMIN>0 is refused outright, and if the gate were relaxed the hardcoded CC.MPS=0 would misprogram it. Widening: replace the == gate with "reject only if 12 < min_page_shift()", and set CC.MPS = min_page_shift()-12 explicitly so it always matches the drive's floor.
Also: transfers are capped at 32 KB with no chunking and MDTS is never read (nvm/constants.rs:23), and both NVMe and AHCI poll every completion with a busy spin instead of waiting on the MSI-X grant that is already bound, which pins a CPU core per I/O. Adding an interrupt-wait path is the biggest storage throughput/efficiency win.
NVMe rejects any controller whose CAP.MPSMIN is not exactly 4K, and never programs CC.MPS. admin/controller.rs:34 returns UnsupportedPageSize unless min_page_shift()==12, then writes CC without setting CC.MPS (bits 7:11), leaving host page size at 4K by default. The computed max_page_shift is never used.
Nearly all real SSDs advertise MPSMIN=0 so the == gate usually passes, but any controller advertising MPSMIN>0 is refused outright, and if the gate were relaxed the hardcoded CC.MPS=0 would misprogram it. Widening: replace the == gate with "reject only if 12 < min_page_shift()", and set CC.MPS = min_page_shift()-12 explicitly so it always matches the drive's floor.
Also: transfers are capped at 32 KB with no chunking and MDTS is never read (nvm/constants.rs:23), and both NVMe and AHCI poll every completion with a busy spin instead of waiting on the MSI-X grant that is already bound, which pins a CPU core per I/O. Adding an interrupt-wait path is the biggest storage throughput/efficiency win.